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NXP Semiconductors /LPC43xx /ADCHS /FIFO_CFG

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Interpret as FIFO_CFG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PACKED_READ)PACKED_READ 0LEVEL0RESERVED

Description

Configures FIFO fill level that triggers interrupt and packing 1 or 2 samples per word.

Fields

PACKED_READ

0 = one sample is packed in one 32-bit read cycle 1 = two samples are packed in one 32-bit read cycle
LEVEL

When the FIFO contains more or equal than FIFO_LEVEL samples interrupt flag FIFO_FULL interrupt will be set and DMA_Read_Req will be raised.
RESERVED

Reserved

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data